![]() I can't get the override to take the value. I can show that this is true when I pass a value at instantiation, for example: #(.MY_STD_LOGIC_GENERIC( 3'd6 )) will equal 'L'it just doesn't seem that vopt interprets the number (positional value) from the command line correctly. Note that this only applies to std_logic types - for std_logic_vector you can simply pass the value as you would normally expect. For example, to set the generic to a ‘U’, use 1’b0, to set it to an ‘X’, use 1’b1, to set it to ‘0’, use 2’b10. To be able to correctly set the VHDL generic to any of the nine states, you must set the value in the Verilog instance to the element (positional) value in the std_logic enum that corresponds to the std_logic value (that is, the position not the value itself). Note that std_logic is defined as a 9-state enumerated type. Passing parameter values from Verilog or SystemVerilog to a VHDL generic of type std_logic is slightly different than other VHDL types. ![]() Why do you say that the value of "2" is not valid? Alex, thank you for your prompt response! ![]()
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